A technology of clock data recovery (CDR) in data communications is required to provide a short lock time when the data are intermittently transmitted (when starts and stops of transmission are repeated). For example, PCI Express adopts CDR with phase interpolator, in order to realize a short lock time (refer to Nonpatent Literature 1). In the CDR with phase interpolator, a receiver generates a plurality of clocks having different phases and selects one of the clocks that has a phase closest to that of the received data. This CDR with phase interpolator has a function to select a clock but no function to adjust a clock frequency. This requires a clock frequency error (offset) to be small between a clock source of a data transmission side and a clock source of a data reception side. For instance, Nonpatent Literature 1 uses an identical clock source in both the data transmission side and the data reception side so as not to produce a clock frequency error.
Moreover, Serial ATA requires a clock source in a data transmission side to have a clock frequency error of ±350 [ppm] whereas requiring a clock source in a data reception side to have a clock frequency error similar to that of the data transmission side. Thereby, the clock frequency error can be small between the clock sources in the data transmission side and the data reception side, so that a short lock time is achieved (refer to Nonpatent Literature 2).
Furthermore, USB specifies that a synchronous pattern having a small bit length is used to lock on the premise that the clock frequency error is small enough in between the clock sources of the data transmission side and the data reception side. To be specific, the clock frequency error needs to be 0.25%, i.e., 0.0025=(0.21 [nsec]/( 1/12 [Mbps]) (refer to Nonpantent Literature 3).
Further, the transmission of video signals uses data communications that transmit data continuously. In such communications, data can be transmitted continuously once the lock is fulfilled. Thus, even if a lock time is long, CDR with phase synchronization is adopted (refer to Nonpatent Literature 4). The characteristic of CDR with phase synchronization is like that in Nonpatent Literature 4. Suppose that the phase comparison needs 500 cycles, for instance. The phase comparison requires the change points of bits while the presence probability of the change points of bits is about 50%. The lock thus needs about 1000 bits. In particular, the clock frequency error as well as the phase error arises at the time when the power is turned on. The lock further needs additional bits so that the necessary number of bits becomes 10,000 bits, for instance. This requires the lock time in CDR with phase synchronization to be shorter as much as possible. For instance, another technology is disclosed which oversamples a bit string of data and conducts signal processing with a digital circuit (refer to Nonpatent Literature 5 and Patent Literature 1).